(a) Field of the Invention
The present invention relates to a gate insulation film having a slanted nitrogen concentration profile and, more particularly, to a MOSFET having a gate insulation film which prevents degradation of the on-current characteristic of the MOSFET.
(b) Description of the Related Art
LSIs (large-scale integrated circuits) are categorized into two types including a memory device and a logic device. Both types of LSIs are generally implemented by MOSFET circuits by taking advantages of higher integration capability and low costs thereof.
As is well known, the operational principle of the MOSFET is such that a control voltage applied to the gate electrode, which is disposed on the semiconductor substrate with an intervention of a gate insulation film therebetween, controls the conductivity of the channel region induced on the surface area of the semiconductor substrate just under the gate insulation film. In this respect, the gate insulation film is the key element of the semiconductor device comprised of the MOSFET circuits, and it is one of the most important issues to form the gate insulation film with higher reliability and superior controllability.
In the recent logic devices, under the circumstances as described above, a silicon oxide (SiO2) film widely used as the gate insulation film has a thickness as low as about 3.0 nanometers (nm), and this thickness becomes further smaller responding to the requirement of higher performances of the logic devices.
The smaller thickness of the gate insulation film involves the problems of increase in the gate leakage current and penetration of impurities through the gate insulation film from the gate electrode. The former results from the degradation of the insulation capability of the gate insulation film due to the smaller thickness. On the other hand, the latter occurs when impurity ions such as boron or phosphorous ions doped in the gate electrode made of polysilicon, for example, readily penetrate the thin gate insulation film during the heat treatment in the fabrication process.
In particular, the latter causes a change or variance in the conductivity of the channel due to the impurity ions reached to the channel by the penetration, whereby the characteristics of the MOSFET such as the drain current and the threshold voltage thereof significantly vary to affect the operation of the MOSFET.
In order to suppress the increase in the gate leakage current, it is effective to use another insulation film having a higher dielectric constant as the gate insulation film instead of the silicon oxide film, as known in the prior art. In order to suppress the impurity penetration, it is effective to dope the silicon oxide film with nitrogen to form a silicon oxynitride (SiON) film. It is known that the silicon oxynitride film has a higher dielectric constant compared to the silicon oxide film. Thus, the silicon oxynitride film has been used in the prior art for suppression of the increase in the gate leakage current and the impurity penetration through the gate insulation film.
Patent Publication JP-A-6(1994)-140392, for example, describes a fabrication process for a semiconductor device, wherein a silicon oxynitride film formed by nitriding a silicon oxide film is used as the gate insulation film. In the described process, nitrogen radicals generated by optical excitation alone or in combination with plasma excitation are used for nitriding the silicon oxide film. In the nitriding step, the optical excitation process provides an energy assistance for the nitriding, whereby even a relatively lower temperature between 700 and 900 degrees C effects the nitriding.
There is a problem in the process as described above that the nitrogen radicals are generated by using the optical excitation, which is generally difficult to control. In addition, an optimum temperature profile with time for the process of introducing the nitrogen radicals into the silicon oxide film is not described therein and is difficult to find. Thus, it is desired to form a silicon oxynitride film with a suitable reproducibility and in-plane uniformity in the fabrication of MOSFETs in a semiconductor device.
FIG. 1 is a sectional view of a typical semiconductor device which may be fabricated by the process described in the above publication, and FIG. 2 is an enlarged partial view thereof.
The semiconductor device includes a p-type silicon substrate 12, an isolation region 13 formed by a STI technique on the silicon substrate 12, a p-well formed in the active region isolated by the isolation region 13, a threshold-controlling well 15 formed in the surface area of the p-well 14, an n-type source region 16 including a lightly doped region 16A and a heavily doped region 16B selectively formed in the threshold-controlling well 15, an n-type drain region 17 including a lightly doped region 17A and a heavily doped region 17B selectively formed in the threshold-controlling well 15, a gate electrode 19 formed on the silicon substrate 12 with an intervention of a gate insulation film 18 therebetween, side-wall insulation films 20 covering the side walls of the gate insulation film 18 and the gate electrode 19, a pair of source/drain electrodes 21 and 22 formed on the n-type source/drain regions 16 and 17, respectively.
In FIGS. 1 and 2, an nMOSFET is exemplified, wherein the n-type source/drain regions 16 and 17 have a so-called LDD (lightly doped drain) structure.
The gate insulation film 18 has a two-layer structure including a silicon oxide film 23 and an overlying silicon oxynitride film 24, as shown in FIG. 2. The overall thickness of the gate insulation film 18 is around 1.75 nm. In fact, the thickness of the silicon oxide film 23 is around 1.6 nm before the silicon oxynitride film 24 is formed by nitriding the silicon oxide film.
FIGS. 3A to 3E show consecutive fabrication steps of a conventional fabrication process for the nMOSFET of FIG. 1. An isolation region 13, a p-well 14 and a threshold-controlling well 15 are first formed on a p-type silicon substrate 12, followed by heat treating the same in a chamber of a single-wafer-processing type, for example. Thus, a silicon oxide film 23 having a thickness of about 1.6 nm is formed on the substrate 12, as shown in FIG. 3A.
Subsequently, nitrogen is introduced into the silicon oxide film 23 to form a silicon oxynitride film 24 on top of the silicon oxide film 23, as shown in FIG. 3B. In this step, the silicon wafer is received in a plasma chamber, after plasma is generated by applying a power source to nitrogen gas to change the same into plasma source including nitrogen atoms and nitrogen radicals. The silicon wafer is heated based on the typical temperature profile having a rising slope 70A having a rising rate of 75 degrees C. per second, a flat peak 70B at 950 degrees C., and a falling slope 70C having a rising rate of 40 degrees C. per second, as shown in FIG. 4.
The power source is turned OFF at the last of the flat peak 70B of the temperature profile. By using the plasma source together with the heat treatment, nitrogen is introduced to the surface area of the silicon oxide film 23 to from a silicon oxynitride film 24 on the silicon oxide film 23. This process is called a rapid thermal process (RTP). The original thickness of the gate insulation film 18 at 1.6 nm is changed to 1.75 nm after the RTP.
Subsequently, a polysilicon (polycrystalline silicon) film 25 is deposited using a CVD technique on the entire surface of the wafer, as shown in FIG. 3C, followed by patterning the polysilicon film 25 and the silicon oxide film 23 together with the silicon oxynitride film 24 by using a known photolithographic technique, to thereby form a gate insulation film 18 and a gate electrode 19, as shown in FIG. 3D.
Thereafter, n-type impurities are introduced by an ion-implantation technique using the gate electrode 19 as a mask to form a lightly doped regions 16A and 17A, followed by forming side-wall insulation films 20 for covering the side walls of the gate electrode 19 and the gate insulation film 18. N-type impurities are then introduced by ion-implantation using the sidewall insulation films 20 and the gate electrode 19 as a mask to form heavily doped regions 16B and 17B, whereby n-type source/drain regions 16 and 17 are formed, as shown in FIG. 3E. Source/drain electrodes 21 and 22 are then formed on the source/drain regions 16 and 17 to complete the nMOSFET of FIG. 1.
FIG. 5 shows concentration profiles of the gate insulation film 18 obtained by secondary ion mass spectroscopy (SIMS). In FIG. 5, atomic percent concentrations of nitrogen, oxygen and silicon in the gate insulation film 18 are plotted on ordinate against the depth in the gate insulation film 18 plotted on abscissa. The SIMS is conducted for evaluation of the film property of the gate insulation film 18, to obtain the concentration profile of any of the elements along the thickness direction of the gate insulation film 18.
As understood from FIG. 5, the nitrogen concentration profile has a maximum at 7 to 8 atomic percents in the vicinity of the top surface of the gate insulation film 18, reduces monotonically from the top surface toward the bottom or silicon substrate 12, and assumes zero in the range between the bottom and the location L1 which is d1 nm (as small as 0.46 nm) apart from the bottom. The area wherein the nitrogen concentration assumes zero is occupied solely by oxygen and silicon atoms of SiO2 film 23.
There is a problem found by the present inventor for the conventional semiconductor device in that the MOSFET has a poor on-current characteristic due to the specific nitrogen concentration profile thereof. More specifically, since the depth d1 is as small as 0.46 nm, the nitrogen content in the vicinity of the surface of the silicon substrate 12 causes that the carriers flowing through the channel region just under the gate insulation film 18 are scattered by the influence of the fixed positive charge, which is generated in the gate insulation film 18 due to the presence of the nitrogen content. This degrades the on-current characteristic of the MOSFET. If the nitrogen content appears in more vicinity of the substrate surface or reaches to the substrate surface, the on-current characteristic is further degraded due to the occurrence of the interface state.
In view of the above, it is an object of the present invention to provide a semiconductor device having a gate insulation film which prevents degradation of the on-current characteristic of MOSFETs.
It is another object of the present invention to provide a method for fabricating such a semiconductor device by controlling the nitrogen concentration profile of the gate insulation film.
The present invention provides a semiconductor device comprising a semiconductor substrate, and a MOSFET formed thereon and including a gate electrode, a gate insulation film and source/drain regions, said gate insulation film including nitrogen, oxygen and silicon atoms as constituent elements thereof, wherein a nitrogen concentration profile of said gate insulation film with respect to a thickness direction thereof has a maximum nitrogen concentration between 10 and 30 percents.
The present invention also provides a method for fabricating a MOSFET comprising the steps of: forming a gate insulation film made of silicon oxide on a semiconductor substrate; introducing nitrogen into said gate insulation film in a plasma ambient including nitrogen to form a silicon oxynitride film, said nitrogen introducing step including a thermal treatment, said thermal treatment using a temperature profile with time including a rising slope rising at a rate between 200 and 400 degrees C. per seconds, a peak temperature between 450 and 1200 degrees C., and a falling slope falling at a rate between 50 and 200 degrees C. per seconds; and forming a gate electrode and source/drain regions in association with said gate insulation film.
In accordance with the MOSFET in the semiconductor device of the present invention, degradation of the on-current characteristic of the MOSFET can be suppressed.
In accordance with the MOSFET manufactured by the method of the present invention, nitrogen can be introduced to the silicon oxide film with a superior controllability, whereby the MOSFET of the present invention can be formed with a higher yield.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.